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Brendan Rankin - 6/9/2006


I really enjoyed reading your article and would love to see things go this way. The biggest challenge, then, is (as you say) bundling all of these components, at the top level.

I've been working in Embedded Apps. at Altera, for the past 2 years (or so), and we're definitely seeing a trend in that direction. I know of several customers that have used discrete SoPC Builder sub-systems for each part of their overall design (some with a small processor, others with simple "state sequencers"). A master processor then just orchestrates the whole thing. It isn't easy (yet...) to design this way, but each customer that's been through this process is now reaping the rewards of this sort of system modularization. The path to upgrade and even radical re-design (of particular modules) has now become less complex.

Of course, FPGAs are a natural for this sort of thing....particularly in the embedded space, but I think it will spread. The Cell architecture requires some very complex build tools in order to stitch together a single "software cell." My feeling is that, once these are tools mature for the Cell, this technology can be applied in other areas. I, for one, would love to see this sort of thing make it into my realm.

Best Regards,

- Brendan

P.S.: If you don't know already, an SoPC Builder sub-system consists of...
Nios II Processor (optional....one Avalon master is necessary, however) and various peripherals connected over the Avalon switch fabric.

Mark Bereit - 6/10/2006


Thank you for your comments! This sort of thing is exactly what I would like to see more of... along with, please, more thought on how to make the process not quite so intimidating to begin!

I have followed Altera's processor cores with interest if not in detail, and I think there are solutions waiting there. I also think that a really cool Altera FPGA costs much more than a really cool MPU. Unless there is more discussion about the approaches, there will remain a perception that unit cost increases, easily quantified, will trump development cost decreases, hard to quantify, hard to defend and (presently) hard to even claim.

So... how do we get there from here?

Mark Bereit

Brendan Rankin - 6/10/2006


My personal feeling is that the top-level "stitching" tools will take a bit longer to gel. Our goal is to make SoPC Builder hierarchical, so that you could have multiple SoPC Builder subsystems, with one top-level system that pulls it all together. This has required us to completely re-design the whole system, with this in mind.

Also, we've recently released an ANSI C to Hardware accelerator (C2H) which should enable quick HW acceleration of critical algorithms....without a lot of VHDL/Verilog expertise.

Regarding cost.... one size doesn't fit all. For extremely simple tasks, nothing will beat a PIC (or the like) and the necessary peripherals. For complex tasks, perhaps combining multiple SoPC Builder-like subsystems is the "best" approach (even from a cost perspective), but the lack of top-level "stitching" and debug tools makes it a very manual process..... That, more than cost, will scare time/risk-adverse projects away, in the short term.

I can, however, easily envision a top-level, processor controlled system driving multiple sub-systems, some with simple "interrupt-less" processors, some with nothing but hardware state machines. As C2H matures, it will enable you to design complete, application specific sub-systems....with little need to understand the hardware level details. This is the whole reason I came to Altera, after playing around with SoPC Builder when I was between jobs. The devil will be in the implementation and delivery of this approach to the market... Like anything new, it takes a few brave souls to break new ground. You'd be pretty amazed what people are doing with the current technology.... Fish-finders, GPS devices, car video/multimedia systems, etc. Presently, this still requires a person with the knowledge of both hardware and software design, but, hopefully, this will change.

I would like to see similar approaches with other processors, but, unfortunately, I don't see it happening (outside of Cell). I'm not sure the other processors are even architected, correctly, to handle this.... There are the custom microprocessor guys, but they don't offer the flexibility of FPGAs. I think, for now, you might see a lot of people prototyping big systems on FPGAs with the idea of moving to ASIC/Structured ASIC when they go to production. All of this sort of design is much harder than what you can do with discrete microprocessors, today.

Here's to hoping that all of this changes! Whether FPGAs (or something that has yet to be invented) drive the change remains to be seen.


- Brendan

Mark Bereit - 6/10/2006


My first thought on reading your comments is to wish I lived close to San Jose, as I'd like to work with you! I love working both sides of the hardware/software divide together but know that's a tough straddle for many.

I am hopeful, too, that the Cell architecture will be enough of a success story to validate the cooperative processing approach and drive more thought in tools that make sense.

Good luck with C2H and SoPC Builder... here's to hoping these ideas catch on!

Mark Bereit